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IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
IDTCV115C
FEATURES:
* * * * * *
DESCRIPTION:
One high precision N and SSC programmable PLL for SRC/PCI One high precision N and SSC programmable PLL for CPU One high precision SSC programmable PLL for SATA One high precision PLL for 96MHz/48MHz Band-gap circuit for differential outputs Support multiple spread spectrum modulation, down and center * Support SMBus block read/write, index read/write * Selectable output strength for REF, PCI, and USB48MHz * Available in SSOP package
IDTCV115C is a 56 pin clock device, complying the latest Intel CK410 requirements, for Intel advance P4 processors. The CPU output buffer is designed to support up to 400MHz processor. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.
KEY SPECIFICATION:
* * * *
CPU/SRC CLK cycle to cycle jitter < 85ps SATA CLK cycle to cycle jitter < 85ps Static PLL frequency divide error < 114 ppm Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
SATA PLL SCC Programmable SATA/ SRC4 - SATA
PCI[4:0], PCIF[2:0] PCI/
14.318MHz Osc
PCIEX PLL SCC N Programmable PCIE/ SRC[6:5] [3:1]
MUX CPU PLL SCC N Programmable
CPU_ITP/ SRC7
Host/
CPU[1:0]
48MHz/
USB48
Fixed PLL No SCC
96MHz/
DOT96
OUTPUT TABLE
CPU 2 CPU_ITP/SRC 1 SRC 5 SATA 1 PCI/PCIF 8 REF 1 DOT96 1 48MHz 1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
(c) 2004 Integrated Device Technology, Inc.
MAY 2004
DSC - 6520/10
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
VDD_PCI VSS_PCI
PCI2 PCI3 PCI4
TEST MODE SELECT(1)
5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 PCI1 PCI0 FS_A VDD_suspend REF0 VSS_REF XTAL_IN XTAL_OUT VDD_REF SCL* SDA*
CPUT0 CPUC0
If TEST_SEL sampled above 2V at VTT_PWRGD active LOW Pin38 (test_mode) 1 0 CPU REF/N Hi-Z SRC REF/N Hi-Z PCI/F REF/N Hi-Z REF REF Hi-Z DOT96 REF/N Hi-Z USB REF/N Hi-Z
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8
VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1
PCIF2
NOTE: 1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N.
VDD_48
USB48MHz
ITP_EN
ITP_EN 1 0 pin 38 CPUC2_ITP SRCC7 pin 39 CPUT_ITP SRCT7
VSS_48
DOT_96 DOT_96#
VDD_CPU
CPUT1 CPUC1
**VTT_PWRGD#/PWRDWN
SRCT1 SRCC1
VSS_CPU IREF FS_B/Test_Mode FS_C/Test _Sel
CPU2_ITP/SRCT7 CPU2_ITP/SRCC7
VDD_SRC VSS
SRCT2 SRCC2 SRCT3 SRCC3
VDD_SRC
SRCT6 SRCC6 SRCT5 SRCC5
VSS_GND
SRCT4_SATA SRCC4_SATA
VDD_SRC
VSS_SRC
* = ~ 130K internal pull-up. ** = ~ 130K internal pull-down.
SSOP TOP VIEW
HW FREQUENCY SELECTION TABLE
FSC, B, A 101 001 011 010 000 100 110 111 CPU 100 133 166 200 266 333 400 Reserve SRC4_SATA 100 100 100 100 100 100 100 100 SRC[3:1], SCR[7:5] 100 100 100 100 100 100 100 100 2 PCI 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 USB 48 48 48 48 48 48 48 48 DOT 96 96 96 96 96 96 96 96 REF 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VDD_PCI VSS_PCI PCI2 PCI3 PCI4 VSS_PCI VDD_PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD_48 USB48 VSS_48 DOT_96T DOT_96C **VTT_PWRGD#/PWRDWN Type PWR GND OUT OUT OUT GND PWR I/0 OUT OUT PWR OUT GND OUT OUT I/O Description 3.3V GND PCI clock PCI clock PCI clock GND 3.3V PCI clock, free running. CPU_2 select (sampled at VTT_PWRGD# assertion), HIGH = CPU_2. PCI clock, PCI clock, 3.3V 48MHz clock GND 96MHz 0.7V current mode differential clock output 96MHz 0.7V current mode differential clock output 3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and PCIF_0/ITP_EN inputs. After VTT_PWRGD# assertion, becomes a real-time input for asserting power down (active high). Internal pull LOW. Differential Serial reference clock Differential Serial reference clock 3.3V GND Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock GND SATA clock SATA clock 3.3V GND Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock Differential Serial reference clock 3.3V Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7 Selectable CPU or SRC differential clock output. ITP_EN=0 @ VTT_PWRGD# assertion = SRC_7 CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted. CPU frequency selection. In test mode, 1=Hi-Z, 0=REF/N. Reference current for differential output buffer GND Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output 3.3V Host 0.7V current mode differential clock output Host 0.7V current mode differential clock output SMBus data
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SRCT1 SRCC1 VDD_SRC VSS SRCT2 SRCC2 SRCT3 SRCC3 VSS SRCT4_SATA SRCC4_SATA VDD_SRC VSS_SRC SRCC5 SRCT5 SRCC6 SRCT6 VDD_SRC CPUC2_ITP/ SRCC7 CPUT2_ITP/ SRCT7 FS_C/Test_Sel FS_B/ Test_Mode IREF VSS CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 *SDA
OUT OUT PWR GND OUT OUT OUT OUT GND OUT OUT PWR GND OUT OUT OUT OUT PWR OUT OUT I/O I/O OUT GND OUT OUT PWR OUT OUT I/O
3
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number 47 48 49 50 51 52 53 54 55 56 Name *SCL VDD_REF XTAL_OUT XTAL_IN VSS_REF REF0 VDD_Suspend FS_A PCI0 PCI1 Type IN PWR OUT IN GND OUT PWR IN OUT OUT Description SMBus CLK 3.3V Xtal output Xtal input GND 14.318 MHz reference clock output In the power down mode, supply 3.3V to SM control registers, <1mA. In the normal operation, regular VDD. CPU frequency selection PCI clock PCI clock
SM PROTOCOL INDEX BLOCK WRITE PROTOCOL
Bit 1 2-9 10 11-18 19 20-27 28 29-36 37 38-45 46 # of bits 1 8 1 8 1 8 1 8 1 8 1 From Master Master Slave Master Slave Master Slave Master Slave Master Slave Master Slave Master Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Byte count, N, (0 is not valid Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Nth data byte Acknowledge Stop
INDEX BLOCK READ PROTOCOL
Bit 1 2-9 10 11-18 19 20 21-28 29 30-37 38 39-46 47 48-55 # of bits 1 8 1 8 1 1 8 1 8 1 8 1 8 From Master Master Slave Master Slave Master Master Slave Slave Master Slave Master Slave
Master can stop reading any time by issuing the stop bit without waiting until Nth byte (byte count bit30-37).
Description Start D2h Ack (Acknowledge) Register offset byte (starting byte) Ack (Acknowledge) Repeated Start D3h Ack (Acknowledge) Byte count, N (block read back of N bytes), Byte 8 Ack (Acknowledge) first data byte (Offset data byte) Ack (Acknowledge) 2nd data byte Ack (Acknowledge) : Ack (Acknowledge) Nth data byte Not acknowledge Stop
Master Slave Master
INDEX BYTE WRITE
INDEX BYTE READ
Setting bit[11:18] = starting address, bit[20:27] = 01h.
4
Setting bit[11:18] = starting address. After reading back the first data byte, master issues Stop bit.
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48)
Str[1:0] 00 01 10 11 2L 1H 1L 2H Multiple loads Recommend Single loads Recommend Recommend Recommend Recommend USB48 Recommend
SSC MAGNITUDE CONTROL, SMC
SMC[2:0] 000 001 010 011 100 101 110 111 % OFF - 0.25 - 0.5 0.125 0.25 0.375 0.5 0.75
PCI
When Byte5 bit6 = 0; otherwise, PCI = SRC frequency/3
PCIS[1:0] 00 01 10 11 PCI 33.33 36.36 40
S_CBS[1:0], H_CBS[1:0] BAND SELECTION
S_CBS/H_CBS[1:0] 00 01 10 11 FS[C,B,A] CB1_[2:0], byte17, CPU PLL Mode selection1 CB2_[2:0], byte17, CPU PLL Mode selection2 Don't care
S_CNS, S_PNS, H_CNS,H_PNS N SELECTION
NS[1:0] 00 01 10 11 Standard of Each CPU Mode (Band) N Selection 1 N Selection 2 Don't care
RESOLUTION
CPU CPU CPU CPU CPU CPU CPU SRC = 100MHz mode = 133MHz mode = 166MHz mode = 200MHz mode = 266MHz mode = 333MHz mode = 400MHz mode (PCI Express) N Resolution (MHz) 0.666667 0.888889 1.333333 1.333333 2.666667 2.666667 2.666667 0.666667 % 0.67% 0.67% 0.8% 0.67% 1.00% 0.8% 0.67% 0.67% N= 150 150 125 150 100 125 150 150
CB1[2:0]. CB2[2:0], CPU MODE SELECTION
CB[2:0] 101 001 011 010 000 100 110 111 CPU Mode, MHz 100 133 166 200 266 333 400 Reserve
5
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 0
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CPUT2, CPUC2/ SRCT7, SRCC7 SRCT6, SRCC6 SRCT5, SRCC5 SRCT4, SRCC4 (SATA) SRCT3, SRCC3 SRCT2, SRCC2 SRCT1, SRCC1 REF0 2x drive Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Output enable 2x drive enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1x 1 Enable Enable Enable Enable Enable Enable Enable 2x Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
BYTE 1
Bit 7 6 5 4 3 2 1 0 Output(s) Affected DOT96T, DOT96C Reserve USB48 Reserve REF0 CPUT1, CPUC1 CPUT0, CPUC0 Reserve Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 0 1 1 1 0 Recommended 0 0
0
BYTE 2
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PCI4 PCI3 PCI2 PCI1 PCI0 PCIF2 PCIF1 PCIF0 Description/Function Output enable Output enable Output enable Output enable Output enable Output enable Output enable Output enable 0 Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate 1 Enable Enable Enable Enable Enable Enable Enable Enable Type RW RW RW RW RW RW RW RW Power On 1 1 1 1 1 1 1 1
BYTE 3
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function FSC latched value on power up FSB latched value on power up FSA latched value on power up SRCT PWRDWN drive mode CPUT2 PWRDWN drive mode CPUT1 PWRDWN drive mode CPUT0 PWRDWN drive mode DOT96 PWRDWN drive mode 6 0 1 Type R R R RW RW RW RW RW Power On
SRCT[7:1] CPUT2 CPUT1 CPUT0 DOT96T
Driven in power down Driven in power down Driven in power down Driven in power down Driven in power down
Tristate in power down Tristate in power down Tristate in power down Tristate in power down Tristate
0 0 0 0 0
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 4
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PCIFStr1 PCIFStr0 PCIStr1 PCIStr0 REFStr1 REFStr0 48MHStr1 48MHzStr0 Description / Function PCIF strength selection see SE Clock Strength table PCI strength selection see SE Clock Strength table REF strength selection see SE Clock Strength table USB48MHz0 strength selection see SE Clock Strength table 0 1 Type Power On 0 0 0 1 0 0 1 1
BYTE 5
Bit 7 6 5 4 3 Output(s) Affected PCIPLLS PCIS1 PCIS0 SM control registers contents Power Down mode SATA_SMC2 SATA_SMC1 SATA_SMC0 Description / Function PCI PLL select See PCIS table, only valid when Byte5 bit 6 = 0 See PCIS Table During the Power Down 0 SATA PLL 1 PCI EX PLL Type RW RW RW RW Power On 0 0 0 1
Reset SM to default
SM contents have no change
2 1 0
SATA PLL spread spectrum magnitude control select see SMC table
RW RW RW
0 1 0
BYTE 6
Bit 7 6 5 4 3 2 1 0 Output(s) Affected WDHRB WDSRB SRC_SMC2 SRC_SMC1 SRC_SMC0 CPU_SMC2 CPU_SMC1 CPU_SMC0 Description / Function Hard Alarm read back, reset by WD disable Soft Alarm read back, rest by WD disable SRC(PCIEXpress) PLL spread spectrum magnitude control select see SMC table CPU PLL spread spectrum control magnitude select see SMC table 0 1 Type R R RW RW RW RW RW RW 0 1 0 1 0 0 Power On
7
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 7
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function Revision ID Revision ID Revision ID Revision ID Vendor ID Vendor ID Vendor ID Vendor ID 0 1 Type Power On 0 0 0 0 0 1 0 1
BYTE 8
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 1 1 1 1
BYTES 9 - 16 ARE DUMMY BITES BYTE 17
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CB1_2 CB1_1 CB1_0 CB2_2 CB2_1 CB2_0 CN1_8, MSB Description / Function CPU PLL Mode Selection 1 See CPU Mode Selection table 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0
CPU PLL Mode Selection 2 See CPU Mode Selection table CPU PLL N selection 1
BYTE 18
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CN1_7 CN1_6 CN1_5 CN1_4 CN1_3 CN1_2 CN1_1 CN1_0, LSB Description / Function CPU PLL N selection 1 0 1 Type RW RW RW RW RW RW RW RW Power On 1 0 0 1 0 1 1 0
8
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 19
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CN2_8, MSB CN2_7 CN2_6 CN2_5 CN2_4 CN2_3 CN2_2 CN2_1 Description / Function CPU N selection 2 0 1 Type Power On 0 1 0 0 1 0 1 1
BYTE 20
Bit 7 6 5 4 3 2 1 0 Output(s) Affected CN2_0, LSB Description / Function CPU N selection 2 0 1 Type Power On 0
PN1_8, MSB PN1_7
RW RW
0 1
BYTE 21
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PN1_6 PN1_5 PN1_4 PN1_3 PN1_2 PN1_1 PN1_0, LSB PN2_8, MSB Description / Function SRC PLL (PCI Express) N Selection 1 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 1 0 1 1 0 0
BYTE 22
Bit 7 6 5 4 3 2 1 0 Output(s) Affected PN2_7 PN2_6 PN2_5 PN2_4 PN2_3 PN2_2 PN2_1 PN2_0, LSB Description / Function SRC PLL (PCI Express) N Selection 2 0 1 Type RW RW RW RW RW RW RW RW Power On 1 0 0 1 0 1 1 0
9
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 23
Bit 7 6 5 4 3 2 1 0 Output(s) Affected S_CBS1 S_CBS0 S_CNS1 S_CNS0 S_PNS1 S_PNS0 Description / Function Soft Alarm CPU PLL mode select, see S_CBS Band Selection Table Soft Alarm CPU PLL N select, see S_CNS N Selection Table Soft Alarm SRC PLL (PCI Express) N select, see S_PNS N Selection Table 0 1 Type RW RW RW RW RW RW Power On 0 0 0 0 0 0
BYTE 24
Bit 7 6 5 4 3 2 1 0 Output(s) Affected H_CBS1 H_CBS0 H_CNS2 H_CNS0 H_PNS1 H_PNS0 Description / Function Hard Alarm CPU PLL mode select, see H_CBS Band Selection Table Hard Alarm CPU PLL N select, see H_CNS N Selection Table Hard Alarm SRC PLL (PCI Express) N select, see H_PNS N selection table 0 1 Type RW RW RW RW RW RW Power On 0 0 0 0 0 0
BYTE 25
Bit 7 6 5 4 3 2 1 0 Output(s) Affected WD Timer 7 WD Timer 6 WD Timer 5 WD Timer 4 WD Timer 3 WD Timer 2 WD Timer 1 WD Timer 0 Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On 0 0 0 0 1 0 1 1
Watchdog timer Default is 11*290ms Hard Alarm = WD timer * 290ms
BYTE 26
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Description / Function 0 1 Type RW RW RW RW RW RW RW RW Power On
Soft Timer 3 Soft Timer 2 Soft Timer 1 Soft Timer 0
Soft Alarm timer Soft Alarm = Soft timer * 290ms
0 0 0 1
10
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 27
Bit 7 6 5 4 3 2 1 0 Output(s) Affected Watch Dog Enable Soft Alarm Enable Reserved Hard Alarm Enable Reserved Hard Alarm FS Relatch Enable Reserved Description / Function Watch Dog Enable Soft Alarm Enable Hard Alarm Enable Relatch FS[C, B, A] at Hard Alarm 0 Disable Disable Disable Disable 1 Enable Enable Enable Relatch Type RW RW RW RW RW RW RW Power On 0 0 0 0 0 0 0
BYTE 42, 43 SRC SPREAD MAGNITUDE (1) BYTE 44 SRC SPREAD CENTER(1) BYTE 38 SRC SPREAD CONTROL SWITCH (FROM BYTE 6 TO BYTES 42, 43, 44)(1)
NOTE: 1. Contact IDT for detailed application note.
11
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PLL FREQUENCY PROGRAMMING PROCEDURES
The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may enable either one or both of the alarms. User presets the CPU PLL Mode and N, and SRC PLL N value: 1. Set CPU PLL Mode, CB1 and CB2, byte 17 2. Set CPU PLL N, CN1 and CN2, byte 18 and byte 19 3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte 21, 22 User selects the frequency for Soft Alarm and Hard Alarm, if enabled respectively: 4. Select Soft Alarm frequency, byte 23 5. Select Hard Alarm frequency, byte 24 User sets the Timer and enables the WD circuit for frequency switch: 6. Set Hard Alarm Timer, byte 25 7. Set Soft Alarm Timer, byte 26 8. Enable Soft and Hard Alarm, byte 27 9. Enable Watch Dog (WDE), byte 27
* *
WDE Disable resets WDSRB and WDHRB. PCI CLK is selectable from SRC PLL or SATA PLL, byte 5 bit 6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI is fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte 5 bit[5:4].
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE Trigger Watch Dog Circuit
If Soft Alarm Enabled (byte 27): Set WDSRB (byte 6) Load CPU N and Mode selections into PCU PLL Load SRC N selection into SRC PLL
If Hard Alarm Enabled (byte 27): Set WDHRB (byte 6) Load CPU N and Band selections into PCU PLL Load SRC N selections into SRC PLL If Hard Alarm Relatch Enabled: Latch FSC, B, A
12
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT PARAMETERS
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%
Symbol VIH VIL VIH_FS VIL_FS IIL IDD3.3OP IDD3.3PD FI LPIN CIN COUT CINX TSTAB Clock Stabilization(2,3) Modulation Frequency(2) TDRIVE_SRC(2) TDRIVE_PD#(2) TFALL_PD#(2) TRISE_PD#(3) TDRIVE_CPU_Stop#(2) TFALL_CPU_Stop#(2) TRISE_CPU_Stop#(3) Input Capacitance(2) Parameter Input HIGH Voltage Input LOW Voltage FS Input HIGH Voltage FS Input LOW Voltage Input LeakageCurrent Operating Supply Current Powerdown Current Input Frequency(1) Pin Inductance(2) Logic inputs Output pin capacitance X1 and X2 pins From VDD power-up or de-assertion of PD# to first clock Triangular modulation SRC output enable after PCI_Stop# de-assertion CPU output enable after PD# de-assertion Fall time of PD# Rise time of PD# CPU output enable after CPU_Stop# de-assertion Fall time of PD# Rise time of PD# 3.3V 5% 3.3V 5% For FSA,B,C and Test_Mode For FSA,B,C and Test_Mode 0< VIN < VDD, no internal pull-up or pull-down Full active, CL = full load All differential pairs driven All differential pairs tri-stated VDD = 3.3V Test Conditions Min. 2 VSS - 0.3 0.7 VSS - 0.3 -5 -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- 14.31818 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD + 0.3 0.8 VDD + 0.3 0.35 +5 400 70 12 -- 7 5 6 5 1.8 33 15 300 5 5 10 5 5 ms KHz ns us ns ns us ns ns pF MHz nH Unit V V V V mA mA mA
NOTES: 1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs. 2. This parameter is guaranteed by design, but not 100% production tested. 3. See TIMING DIAGRAMS for timing requirements.
13
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 2pF
Symbol ZO VOH3 VOL3 VHIGH VLOW VOVS VUDS VCROSS(ABS) d - VCROSS ppm Parameter Current Source Output Impedance(2) Output HIGH Voltage Output LOW Voltage Voltage HIGH(2) Voltage LOW(2) Max Voltage(2) Min Voltage(2) Crossing Voltage (abs)(2) Crossing Voltage (var)(2) Long Accuracy(2,3)
Variation of crossing over all edges
Test Conditions VO = VX IOH = -1mA IOL = 1mA Statistical measurement on single-ended signal using oscilloscope math function Measurement on single-ended signal using absolute value
Min. 3000 2.4 -- 660 -150 -- -300 250 -- -300 2.4993 2.9991 3.7489 4.9985 5.9982 7.4978 9.997 10.4135 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.912 10.1635 175 175 -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- 0.4 850 150 1150 -- 550 140 300 2.5008 3.0009 3.7511 5.0015 6.0018 7.5023 10.003 10.4198 -- -- -- -- -- -- -- -- 700 700 125 125 55 100 85
Unit V V mV mV mV mV ppm
See TPERIOD Min. - Max. values 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread
TPERIOD
Average Period(3)
200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100MHz nominal/spread 96MHz nominal 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100MHz nominal/spread 96MHz nominal
ns
TABSMIN
Absolute Min Period(2,3)
ns
tR tF d-tR d-tF dT3 tSK3 tJCYC-CYC
Rise Time(2) Fall Time(2) Rise Time Variation(2) Fall Time Variation(2) Duty Cycle(2) Cycle(2)
VOL = 0.175V, VOH = 0.525V VOL = 0.175V, VOH = 0.525V
ps ps ps ps % ps ps
Measurement from differential waveform VT = 50% Measurement from differential waveform
45 -- --
Skew(2) Jitter, Cycle to
NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
14
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 30pF
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 tSK1 tJCYC-CYC Rise Time(1) Fall Time(1) Duty Cycle(1) Skew(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 33.33MHz output nominal 33.33MHz output spread IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 29.991 29.991 2.4 -- -33 -- 30 -- 1 1 0.5 0.5 45 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 30.009 30.1598 -- 0.55 -- -33 -- 38 4 4 2 2 55 500 250 V/ns V/ns ns ns % ps ps mA V V mA Unit ppm ns
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS, 48MHZ, USB
Symbol ppm TPERIOD VOH VOL IOH IOL Parameter Long Accuracy(1,2) Clock Period(2) Output HIGH Voltage Output LOW Voltage Output HIGH Current Output LOW Current Edge Rate(1) Edge Rate(1) tR1 tF1 dT1 Rise Time(1) Fall Time(1) Duty Cycle(1) Test Conditions See Tperiod Min. - Max. values 48MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V VOH at Max. = 3.135V VOL at Min. = 1.95V VOL at Max. = 0.4V Rising edge rate Falling edge rate VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Min. -- 20.8257 2.4 -- -29 -- 29 -- 1 1 1 1 45 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 20.834 -- 0.55 -- -23 -- 27 2 2 2 2 55 V/ns V/ns ns ns % mA Unit ppm ns V V mA
NOTES: 1. This parameter is guaranteed by design, but not 100% production tested. 2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
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IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, Supply Voltage: VDD = 3.3V 5%; CL = 10 - 20pF
Symbol ppm TPERIOD VOH VOL IOH IOL tR1 tF1 tSK1 dT1 tJCYC-CYC Parameter Long Accuracy(1) Clock Period Output HIGH Voltage(1) Output LOW Voltage(1) Output HIGH Current(1) Output LOW Current(1) Rise Time(1) Fall Time(1) Skew(1) Duty Cycle(1) Jitter(1) Test Conditions See Tperiod Min. - Max. values 14.318MHz output nominal IOH = -1mA IOL = 1mA VOH at Min. = 1V, VOH at Max. = 3.135V VOL at Min. = 1.95V, VOL at Max. = 0.4V VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VT = 1.5V VT = 1.5V VT = 1.5V Min. -- 69.827 2.4 -- -33 30 1 1 -- 45 -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. 300 69.855 -- 0.4 -33 38 2 2 500 55 1000 Unit ppm ns V V mA mA ns ns ps % ps
NOTE: 1. This parameter is guaranteed by design, but not 100% production tested.
16
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before turning off the VCO. In PD de-assertion all clocks will start without glitches.
PD, POWER DOWN
PWRDWN 0 1
CPU Normal IREF * 2 or float
CPU# Normal Float
SRC Normal IREF * 2 or float
SRC# Normal Float
PCIF/PCI 33MHz Low
USB 48MHz Low
DOT96 Normal IREF * 2 or float
DOT96# Normal Float
REF 14.318MHz Low
PD ASSERTION
PWRDWN
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
17
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD DE-ASSERTION
tSTABLE <1.8mS PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818 tDRIVE_PWRDWN <300S, <200mV
18
IDTCV115C PROGRAMMABLE FLEXPCTM CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDTCV XXX Device Type XX Package X Grade Blank Commercial Temperature Range (0C to +70C) Small Shrink Outline Package SSOP - Green Programmable FlexPCTM Clock for P4 Processor
PV PVG 115C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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